Features Single chip ATM and POS User-Network Interface that supports 1x2488.32 Mbit/s or a combination of up to 4x622.08 Mbit/s and 155.52 Mbit/s. Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432. Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC 2615(1619)/1662 of the PPP Working Group of the Internet Engineering Task Force (IETF). Processes a duplex bit-serial 2488.32 Mbit/s STS-48 (STM-16) data stream with on-chip clock and data recovery and clock synthesis. The STS-48 (STM-16) stream may contain an STS-48c (AU4-16c) or a combination of STS-12c (AU-4-4c) and STS-3c (AU-4). Processes up to four duplex bit-serial 622.08 Mbit/s STS-12 (STM-4) data streams with on-chip clock and data recovery and clock synthesis. Each STS-12 (STM-4) may contain a single STS-12c (AU-4-4c) or up to four STS- 3c (AU-4). Processes up to four duplex bit-serial 155.52 Mbit/s STS-3 (STM-1) data streams with on-chip clock and data recovery and clock synthesis. Each STS-3 (STM-1) may contain a single STS-3c (AU-4). Permits mixed OC-12 and OC-3 data streams.Complies with Telcordia GR-253-CORE jitter tolerance, jitter transfer, and intrinsic jitter criteria. Provides termination for SONET Section, Line, and Path overhead or SDH Regenerator Section, Multiplexer Section, and High Order Path overhead. Provides cross bar functionality to swap STS-12 and STS-3 clients to/from different line-side interfaces.Provides support for automatic protection switching via a 4-bit LVDS 777.6 MHz port.Provides cross bar functionality to swap STS-12 and STS-3 lines and/or clients to/from different APS interfaces.Provides UTOPIA Level 3 32-bit wide System Interface (clocked up to 104 MHz) with parity support for ATM applications.Provides SATURN POS-PHY Level 3 (32-bit System Interface (clocked up to 104 MHz) for Packet over SONET (POS) or ATM applications.Supports independent loop-timed operation for each transmit serial stream. Supports independent line loop back from each line side receive stream to the corresponding transmit stream and independent diagnostic loop back from the line side transmit stream to the corresponding line side receive stream interface. Provides PRBS-23 generator/monitor for off-line link verificationProvides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.Provides a generic 16-bit microprocessor bus interface for configuration, control, and status monitoring. Low power 1.8V CMOS core logic with 3.3V CMOS/TTL compatible digital inputs and digital outputs. PECL inputs and outputs are 3.3V compatible. Industrial temperature range (-40°C to +85°C).500-ball UBGA package.
Typical Applications include:
ATM and Multi-service switches, routers, and switch/routers. SONET/SDH Add/Drop Multiplexers with data processing capabilities.Uplink cards.SONET/SDH ATM/POS Test Equipment.
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